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BIOS[basic input/output system]. Rom ,bios another key component of the mother board. WHY BIOS? by itself CPU is variety incapable of commutating with the individual components of a system. the CPU has only so many commands it is capable of handiling,most devices have their own set of commands that control them. the bios is a collection of very small programs   permanently stored on a ROM chip. which can be accessed from the computer on startup. these programs interpret the data comings from other devices and convert it into the commands the cpu can use. ARCHITECTURE. bios has changed very little over the years in its physical form. three basic chips that have been used for the storage of bios. ERASABLE PROGRAMMABLE ROM(EPROM).use two transistors the floating gate and the control gate. to program the chip a low voltage is applied which connects the chip a low voltage is applied which connects floating gate, and the control gate resulting in the binary equivalent of a one. if sufficient charge is supplied. insufficient charge results in a ‘o’. exposure  to ultra violet [uv] radiation all charges in chop will drains and is not usable further in future. in the beginning manufactures  use a window  shaped quartz by labeling with a foil and then programmed the chip  with a special instrument. EARASABLE PROGRAMMABLE ROM’S[EPROM]:by applying  electric charge on the chip ,it follows to reprogram the bios chip with the usage of a special equipment .but  it  results the problem of obsolescence, they were not a convenient solution. ELECTRICALLY ERASABLE PROGRAMMABLE ROM’S[EEPROM].A step forward in the technology of eprom resulted EEPROM .which uses electric charge to discharge the bios from the previous memory and allow to program again by rewritten a bit at a time. Which process very low and slow. FLASH EPROM: flash ram addresses that issue by rewriting data in blocks of 512 bytes .rewriting   the entire contents can be done so quickly. That this is not an issue nearly all computers manufactured today use flash ROM for their bios. BASIC SERVICES:ROM POST: IT is one thing to have an understanding of how different components of the system perform their functions after the system is up and running but  unfortunately a great deal of system diagnostics must be done because the system isn’t  working. The computer system pulls itself from dormancy to full functionality when it is first  turned on. This is done through a process called power on self test [post].post is function of the ROM-bios chip. When CPU is powered on it first executes the code at memory address ‘FFFFo’(hex)which  is default on most IBM–compatibilities .the first  step in what is known  as the boot process. the first step of post is to perform a system check to make sure all components are properly functioning .while checking the main road functions  the video system is not yet up and running. therefore if anything  fails to properly  initialize. the ROM-bios sends a series of beeps to the computer speakers. to inform that something  has failed. The next step may vary depending  on whether the bios is logged and play or not. The plug and play bios will scan and play the system ,looking the i/o addresses IRQ lines and DMA channels needed by plug and play or complaint devices. a data base of these  resources sometimes referred to as the extended and stored. Next video memory locations on ROM are scanned and a search is made for both  on board and external video adapters. after this adaptor has successfully initialized .the system will display a prompt t#MAIN MEMORY: computers use many different kinds of memory. Most modern CPU contain anywhere from 8k to 64k of a type of memory called level1 (L1), cache used to store frequently used commands or data. When CPU requires a piece of data, the first place it looks is in the cache. It is located into the processor and runs at processor speed but its limitation is the size. It can hold certain amount of information only. To increase the performance a second level of cache L2 can be integrated onto the motherboard of CPU. It is the second place the CPU looks for data. Similarly video cards and hard drives have cache memory. Even some SCSI adapters and sound cards have their own memory. The memory that makes the whole thing work is the RAM installed on the motherboard. It is the location from where all programs run and all files are accessed. RAM is the best known form of computer memory. It is referred as “random access memory”. à How memory works: similar to a microprocessor a memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. Regardless the technology used in the construction of memory basic design is constant in any type of memory, a large grid of cells is designed into the circuit. // a circuitry known as “memory control circuit (MCC)” is used to access data stored in memory. The circuit is activated by the prefetch registers on the CPU. On early PCs this was a separate chip called the memory control chip. àRAM Technoloies: DRAM: the most common form of computers memory is dynamic random access memory (DRAM). The circuit grid of a single dynamic RAM chip consists of an array of microscopic transistors coupled with capacitors. A transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information 0 or 1. // a capacitor is like small bucket that is able to store electrons. To store 1 in the memory cell, the bucket is filled with electrons. To store 0 it is emptied. The problem with the capacitor’s bucket is, it has a leak. Chips are designed around their refresh requirement and a particular terminology has evolved. Particular chips are said to have a 4k refresh, a 2k refresh, or 1k refresh. This determines how many columns there are in a chip that needs to be refreshed. A 4k chip has 4,000 columns, a 2k chip has 2000 columns and 1k chip has 1,000 columns. Capacity of chip is determined by three factors.  Capacity=sit width* columns * rows.          READ AND WRITE PROCESS: DRAM works by sending a charge through the appropriate column (CAS) to activated the transistor at each bit in the column. While writing, the row lines contain the state the capacitor should take on. While reading. The sense amplifier determines the level of charge in the capacitor. If it is more than 50 percent, it reads as 1 otherwise it reads it as 0. the counter tracks the refresh sequence based on which rows have been accessed. The time required for all this is so short expressed in nanoseconds. A memory chip rating of 70 ns means that it takes 70 nanoseconds to completely read and recharge each cell. SRAM: Static RAM is a different kind of memory used as cache memory. It uses a completely different technology. It uses only transistors in its circuitry the form of flip-flop. Each flip-flop holds each bit of memory. A flip-flop for a memory cell takes four or six transistors. A charge representing a bit is permanently stored as long as power is supplied to the circuit. And the constant need for refresh is eliminated. This makes static RAM significantly faster than dynamic RAM. But a static memory cell takes up lot more space on a chip than a dynamic memory cell. Because it has more parts. Therefore we get less memory per chip and that makes static RAM more expensive. MEMORY CHIPS AND MODULES: over the year’s the manufactures have improved memory design, which is becoming more and more sophisticated not pure in addition to this improvements and made in the way memory modules were assembled. àDIPP: In the earliest days of computers memory was installed in a single chip at a time using a package called a “dual inline pin package (DIPP)”. The limitation of this package was that only a single DRAM chip fit onto it. àSIPP: the first attempt at combining multiple DRAM chips into a single module resulted in a single inline pin package(SIPP).  The chip were mounted on circuit boards. The design took up less space on the system board. But installing these modules was difficult. àSIMM: SIPPs were replaced by a package called “single inline memory module”. This memory board used a 30 pin connector and about 3.5* 7.5 inches in size. In most computers we have to install two SIMMs to get 16MB total RAM. As system bus could handle 16 bits at a time. àDIMM: AS PROCESSOR GREW IN SPEED AND BANDWIDTH CAPABILITY the industry adopted a new standard that is “Dual in line memory module”. Dimm from being inserted backward in the socket, and identifies the voltage of DIMM and its underlying technologies. MEMORY TYPES: FPMDRAM:  the earlist types of DRAM wre compatible with slower CPUs. When CPUs became faster, it became necessary to speed up the data transfer from memory to CPU. The first improvement is “first page mode” DRAM. FPM is differed from earlier DRAM in how data was accessed. For every request the CPU made for data RAS  find the appropriate row then  CAS locate the required data. EDO DRAM: extended data out DRAM came in 1994 and is very similar to FPM it is about 5% faster than FPM as there is no delay between read operations. It does not wait for al the processing of the first data before continuing to the next one. As soon as the address of the first data is located EDO RAM start looking for the next data. Maximum transfer rate to L2 cache is approximately 264 MBps. SDRAM: release of synchronous DRAM changed the basic architecture of the DRAM that is a large portion of the memory control chip circuitry, has been moved from the chipset to the SDRAM module itself. Now information in RAM is available to the CPU on every single clock cycle. DDR SDRAM: Double data rate synchronous dynamic  RAM is just like SDRAM except that it has higher bandwidth, meaning greater speed. Maximum transfer rate to L2 cache is approximately 1,064 MBps. RDRAM: Rambus dynamic random access memory designed by Rambus technologies, in cooperation with intel corporation. RDRAM uses a Rambus in line memory  module which is similar in size and pin configuration to a standard DIMM. It uses special high-speed data bus called the rambus channel. VRAM: Video RAM, also known as multiport dynamic random access memory is a type of RAM used specifically for video adapters or 3D accelerations. SGRAM: Synchronous graphics RAM is a less expensive approach to speeding up memory, access for graphics functions. It is not dual-ported as is VRAM therefore cheaper but performance is somewhat lower .#SYSTEM RESOURCES: ‘System resources ‘ are resources that are electrically used by hardware, allocated by firmware and then used by software. There are several devices and applications which may attempt to use the same resource and cause trouble. The four areas that can suffer from resource conflicts are memory addresses, I/O ports, IRQ lines, and DMA channels. *DMA CHANNELS: the best way to speed up system performance is to relieve the microprocessor from all its housekeeping activities. Among them more time consuming is moving blocks of memory inside the computer. For example shifting bytes from a hard disk to main memory. The DMA channel was originally designed for such purpose. It is used to transfer data to and from memory using a chip/device DMA controller without going through the main processor. This specialized chip only needs to know the location of bytes to be moved, the address to go and no. of bytes to move once. Once it receives these information from the processor the DMA controller takes control and does all that job itself. The following table summarizes functions that are commonly for 7 DMA  channels. DMA channel , Data width, Function.  0 , 8 or 16bits, Audio; 1,8 or 16 bits, Audio LAN; 2, 8 or 16 bits, Floppy Disk; 3, 8 or 16 bits, LPT; 4, 16 bits, Cascade Channel; 5, 16 bits, Not assigned; 6, 16 bits, Not assigned; 7, 16 bits, ISA IDE(HDD Controller).// DMA channels have configuration problems as fewer devices use them therefore fewer problems occur. On the other hand, no software tool can detect DMA usage and the hardware tools can detect DMA usage only for ISA  cards and devices. For this reason, it is even more important to read the hardware documentation thoroughly. *IRQ INTERRUPT REQUEST LINE: the purpose of IRQ line is to provide the system with a way to allow a device to work in the background and request the CPU’S attention when it is needed. Many devices use this resource but not all. Usually, if a device is designed to perform tasks independent of the CPU, it will need an IRQ line to alert the CPU when task is done or attention is needed. A mouse and a network card are devices that always use an IRQ. // to extend the capabilities of the interrupt system PCs use an interrupt controller chip to manage several interrupt signals and sets priority for which interrupt is serviced first. On the original IBM PC  the 8259 IRQ controller chip is used. This chip handled only 8 interrupt signals numbered 0 to 7 and assigns each one in a decreasing priority as the numeric designation increases. The interrupts assignments are as follows. IRQ No, Function, IRQ No, Function. 0, timer, 4, com1/com3; 1, keyboard, 5, Hard Disk; 2, EGA display, network, 6, Floppy disk; 3, com2/com4, 7, LPT1; // these 8 bit bus survived inside many Pc’s until a few years ago. Later it is proved that for complex systems 8 interrupts are inadequate. When IBM introduced its advanced technologies “ Pc-at” added a second IC chip 8259 to the motherboard and nearly doubled IRQ  numbers. The 2 nd chip was cascaded to the first one in such a way that output of the new chip connected to the input of the old one, the output of which in tern connected to the microprocessor, this arrangement continued though the latest Pentium type system. Following figure shows total IRQ and its function(fig). example:  the following example of modern communication illustrates how interrupts works, and when they are used. For example a file through internet has to be downloaded. First the program has to be split into two parts. So that one part could perform user tasks in the foreground. While the second part the file download routine could be written as a separate program, calls an” interrupt service routine(ISR) that could run in the background. When the first character of the download comes in. it would cause the following actions: 1. the serial port receives the character from the modem and turns on the appropriate IRQ line. 2. The IC chip on the motherboard passes it on to the CPU if no other interrupts in progress, or pending IRQ of higher priority. 3. when the CPU sees an  IRQ, it stops the foreground task at the end of the current instruction and saves the location of the next instruction to be run for the foreground task. 4. the CPU queries the IC to find out which ISR should be run and there turns control over to that ISR. 5. the IS disables any further interrupts while it is in process and save any interval registers that may modify in the next step. 6. the ISR gets the charcter from the serial port and sends it to the file system. 7.  the ISR finishes by restoring internal registers saved previously and re enables interrupts as control return to the foreground task. 8.  The foreground task continues with the next instruction by restoring internal registers saved before the interrupt. *Sharing IRQs:  When IBM first designed the PC,  the designer’s original intent was to allow IRQs to be shared. The ISA compatibility bus made this provision by allowing two devices to use the same interrupt to draw attention of the microprocessor. The newer bus standards included in their design that all cards must be able to share IRQ s but also must be configurable through software, so that if a conflict occurs software could change the resource and solve the problem. IBM initiated this technique with its MCA bus, which was also used by EISA and PCI. *IO PORTS: every device in Pc uses at least one I/O  port address. In most cases a single device uses 4,8 or 16 I/O port addresses. These port addresses are used to do the following 1. send commands to the device. 2. set, check and clear device interrupts. 3. get device information and status. 4. send and receive data. // I/O port conflicts problems is usually with the older ISA cards. When an ISA  card or device is installed that can neither report its I/O port usage nor be configured by the BIOS. Newer ISA cards that are PnP compatible can be automatically reconfigured by the O/S and usually not involved in conflicts. // I/O port conflicts are similar to memory address conflicts. Actually I/O port addresses signals are carried on the same wire as the memory address bus, with one additional wire to tell the CPU THAT it is an I/O operation not a memory operation. This is referred as IO/MEM wire. The first 10 bits of address bus are used to specify the I/O port address. Which allows for 1,024 distinct addresses.000h through 3FFh. #ARCHITECTURE OF PENTIUM PROCESSOR:  (fig):  CPU registers: these  are small groups of RAM bits inside the processor, which hold the data that is to be operated on by the ALU or FPU. The size of the register is responsible for the type of data and instructions that can be used by the processor. Early models in the PC family had 16- bit CPU registers, they could only run 16 bit software such as  DOS and Windows 3.x the 80386 was the first model to contain 32 bit CPU registers and so it could run 32 bit software. All 386, 486 and the first Pentium CPUs were limited to 32 bit registers, while the Pentium MMX and later Pentium II CPUs had some additional 128 bit registers that allowed the ALU to operate on multiple 32 bit registers that allowed the ALU to operate on multiple 32 bit numbers with a single instruction. This  technique is called “ single instruction, multiple data”. Arithmetic/Logical Unit: this is the heart of every CPU. The ALU is the part that actually performs each instruction such as fetch data from memory into a register, store data from a register to memory, perform an arighmetic or logical function on the data in a register, cause a program action based on the data in a register. Earlier generation processors 8088 and 286 would take several clock cycles to perform each instruction, later ALU designs are able to perform one or more instructions per clock cycle. Instruction decode Unit: this is the portion of the CPU that actually decodes the instruction as it comes into the processor. The newest Pentium designs actually include multiple instruction decode units, to decode instructions from multiple ALUs. Bus control Unit: the bus control unit is simply the portion of CPU that controls activity on the external bus of CPU. This portion of the CPU direct interfaces to the mother board so always runs at motherboard speed. Floating Point Processing Unit: from the 8088 through the 80386, the FPU was an external chip that was plugged into its own socket. Form the 486,m all CPUs except 486SX have the FPU built into the CPU core. Level -1 Cache and Level -2 Cache: a memory cache is used to keep track of the most frequently and most recently used locations from the slower main memory. When the cache contains the data needed by the CPU, there is no waiting and it is called ‘cache-hit’. When the cache does not contain the data it is called ;’cache-hit’ then CPU have to wait until data is delivered y slower main memory. // initially, 386 motherboard designs used 64K SRAM as ‘motherboard cache’ and yielded 9-0 percent cache-hit rate. Next generation of processor chip and mother board is no longer used. // in the Pentium and later processors the level -1 cache was spitted into two parts. I cache dedicated to hold instruction only and D cache. Dedicated to hold data only. It is more efficient than using a single large cache for both instructions and data. The latest Pentium II, III and 4 CPUs are having 1.1 and 1.2 cache in the CPU itself not on the mother board. Front-side Bus: from Pentium II, the bus connection between the CPU and the mother board has received a new name the  front side bus. More recent developments with advanced motherboard DRAM designs called RDRAM and DDR-SDRAM have resulted in some newer terms and specifications for the FSB. DDR-SDRAM is currently available for 200 MHz and 266 MHz FSB speeds. RDRAM is available in FSB speeds of 600, 700 and 800- MHz. Back-side bus: the back side bus is simply a complement to the front side bus for the level-2 cache. While front-side bus describes the interface between the level-2 cache on the processor to the mother board, the back side bus describes the interface between the level-1 cache in the processor core and level -2 cache. #THE IDE INTERFACE:  the peripherals/components must be interfaced to the host system so that they may communicate with each other. Drives are considered to be peripherals and need interface to connect with the computer. Integrated drive electronics (IDE) is most cost effective interface scheme that can support hard drives, CD-ROM drives, DVD-ROM drives and almost any other drive devices. // IDE interface underwent several distinct stages of evolution between the time of first hard cards and the drive systems used today. àThe ATA standard: the IDE interface has many names. The original name for the interface used by IDE drives is the “AT attachment (ATA)” interface named for the IBM AT computer that first introduced the 16 bit ISA bus. Today the ATA interface is the industry standard. The ATA standards are designed by Technical committee T13 of the national committee on information technology standards the T13 committee is an independent association of representatives from major manufacturers of PCs, storage devices and other computer components. à The ATA-2 standard: this standard was published in 1996 and approved by ANSI called the “AT attachment interface with extensions”. Along with ATA-2 is largely regarded as a significant improvement to ATA1 it defines faster PIO DMA data transfer modes. The standard adds more powerful drive command such as the identified Drive command to support auto identification in CMOS. The standard also introduces power management functions, block mode data transfers. àATA-3: the ATA-3 standard was published in 1997 and was approved by ANSI called “ attachment -3 interface” its intension is to increase the reliability of the IDE interface  by introducing the use of bus terminator at both ends of the IDE cable to reduce noise. #THE SCSI INTERFACE:   the small computer systems interface (SCSI) is the second most popular PC drive interface. It is generally considered as more devices and more types of devices. Scsi is better suited to network environment. SCSI was originally designed to be a hard drive interface but supports other types of devices came later. àthe SCSI bus: scsi devices are connected to the host adapter in a daisy chain fashion internal devices use a single rigbon cable with multiple in connectors. One among them connects to the internal connector on the adapter and the rest of which connects to the various devices inside the computer. Where as external devices have two connectors on them and they use separate SCSI cable to connect first device to the external connector on the host adapter, the second device to the first and so on. à SCSI ids: IDE channels are limited to two devices because they use a simple binary circuit to differentiate between the two. Commands intended for one device have a value of 0 on that circuit and commands for the other have a value of 1. where as SCSI can have a total of 8 or 16 devices on the bus depending on its type. // the ID s assigned to the devices on  SCSI bus can be important to the performance of the system, because the ID indicates the priority with which the device is granted access to the bus. Higher numbers have the higher priority. Similarly IDs assigned to devices should be based on their functions, relative speeds and their importance to the system. #SCSI Vs IDE   1. ultra 3 wide SCSI  runs at 160 MB/sec and Fast ATA/66 IDE runs at 66 MB/sec. 2. IDE is basically hard drive interface but can accept other types of devices. SCSI was designed to accept a wide variety of internal and external devices. 3. IDE is single threaded interface means it can only handle one command at a time. If two processes are accessing different devices on the same IDE channel they have to access the system alternatively. 4. copying data from a hard disk to a CD using one IDE channel requires the system to continually access one device and then the other whereas SCSI devices can both be running at the same time. 5. IDE can perform excellently and provides access to basic peripherals like CD-ROM drives. SCSI is the better choice network systems when we want to connect lot of devices to the system. 

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BIOS[basic input/output system]. Rom ,bios another key component of the mother board. WHY BIOS? by itself CPU is variety incapable of commutating with the individual components of a system. the CPU has only so many commands it is capable of handiling,most devices have their own set of commands that control them. the bios is a collection of very small programs   permanently stored on a ROM chip. which can be accessed from the computer on startup. these programs interpret the data comings from other devices and convert it into the commands the cpu can use. ARCHITECTURE. bios has changed very little over the years in its physical form. three basic chips that have been used for the storage of bios. ERASABLE PROGRAMMABLE ROM(EPROM).use two transistors the floating gate and the control gate. to program the chip a low voltage is applied which connects the chip a low voltage is applied which connects floating gate, and the control gate resulting in the binary equivalent of a one. if sufficient charge is supplied. insufficient charge results in a ‘o’. exposure  to ultra violet [uv] radiation all charges in chop will drains and is not usable further in future. in the beginning manufactures  use a window  shaped quartz by labeling with a foil and then programmed the chip  with a special instrument. EARASABLE PROGRAMMABLE ROM’S[EPROM]:by applying  electric charge on the chip ,it follows to reprogram the bios chip with the usage of a special equipment .but  it  results the problem of obsolescence, they were not a convenient solution. ELECTRICALLY ERASABLE PROGRAMMABLE ROM’S[EEPROM].A step forward in the technology of eprom resulted EEPROM .which uses electric charge to discharge the bios from the previous memory and allow to program again by rewritten a bit at a time. Which process very low and slow. FLASH EPROM: flash ram addresses that issue by rewriting data in blocks of 512 bytes .rewriting   the entire contents can be done so quickly. That this is not an issue nearly all computers manufactured today use flash ROM for their bios. BASIC SERVICES:ROM POST: IT is one thing to have an understanding of how different components of the system perform their functions after the system is up and running but  unfortunately a great deal of system diagnostics must be done because the system isn’t  working. The computer system pulls itself from dormancy to full functionality when it is first  turned on. This is done through a process called power on self test [post].post is function of the ROM-bios chip. When CPU is powered on it first executes the code at memory address ‘FFFFo’(hex)which  is default on most IBM–compatibilities .the first  step in what is known  as the boot process. the first step of post is to perform a system check to make sure all components are properly functioning .while checking the main road functions  the video system is not yet up and running. therefore if anything  fails to properly  initialize. the ROM-bios sends a series of beeps to the computer speakers. to inform that something  has failed. The next step may vary depending  on whether the bios is logged and play or not. The plug and play bios will scan and play the system ,looking the i/o addresses IRQ lines and DMA channels needed by plug and play or complaint devices. a data base of these  resources sometimes referred to as the extended and stored. Next video memory locations on ROM are scanned and a search is made for both  on board and external video adapters. after this adaptor has successfully initialized .the system will display a prompt t#MAIN MEMORY: computers use many different kinds of memory. Most modern CPU contain anywhere from 8k to 64k of a type of memory called level1 (L1), cache used to store frequently used commands or data. When CPU requires a piece of data, the first place it looks is in the cache. It is located into the processor and runs at processor speed but its limitation is the size. It can hold certain amount of information only. To increase the performance a second level of cache L2 can be integrated onto the motherboard of CPU. It is the second place the CPU looks for data. Similarly video cards and hard drives have cache memory. Even some SCSI adapters and sound cards have their own memory. The memory that makes the whole thing work is the RAM installed on the motherboard. It is the location from where all programs run and all files are accessed. RAM is the best known form of computer memory. It is referred as “random access memory”. à How memory works: similar to a microprocessor a memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. Regardless the technology used in the construction of memory basic design is constant in any type of memory, a large grid of cells is designed into the circuit. // a circuitry known as “memory control circuit (MCC)” is used to access data stored in memory. The circuit is activated by the prefetch registers on the CPU. On early PCs this was a separate chip called the memory control chip. àRAM Technoloies: DRAM: the most common form of computers memory is dynamic random access memory (DRAM). The circuit grid of a single dynamic RAM chip consists of an array of microscopic transistors coupled with capacitors. A transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information 0 or 1. // a capacitor is like small bucket that is able to store electrons. To store 1 in the memory cell, the bucket is filled with electrons. To store 0 it is emptied. The problem with the capacitor’s bucket is, it has a leak. Chips are designed around their refresh requirement and a particular terminology has evolved. Particular chips are said to have a 4k refresh, a 2k refresh, or 1k refresh. This determines how many columns there are in a chip that needs to be refreshed. A 4k chip has 4,000 columns, a 2k chip has 2000 columns and 1k chip has 1,000 columns. Capacity of chip is determined by three factors.  Capacity=sit width* columns * rows.          READ AND WRITE PROCESS: DRAM works by sending a charge through the appropriate column (CAS) to activated the transistor at each bit in the column. While writing, the row lines contain the state the capacitor should take on. While reading. The sense amplifier determines the level of charge in the capacitor. If it is more than 50 percent, it reads as 1 otherwise it reads it as 0. the counter tracks the refresh sequence based on which rows have been accessed. The time required for all this is so short expressed in nanoseconds. A memory chip rating of 70 ns means that it takes 70 nanoseconds to completely read and recharge each cell. SRAM: Static RAM is a different kind of memory used as cache memory. It uses a completely different technology. It uses only transistors in its circuitry the form of flip-flop. Each flip-flop holds each bit of memory. A flip-flop for a memory cell takes four or six transistors. A charge representing a bit is permanently stored as long as power is supplied to the circuit. And the constant need for refresh is eliminated. This makes static RAM significantly faster than dynamic RAM. But a static memory cell takes up lot more space on a chip than a dynamic memory cell. Because it has more parts. Therefore we get less memory per chip and that makes static RAM more expensive. MEMORY CHIPS AND MODULES: over the year’s the manufactures have improved memory design, which is becoming more and more sophisticated not pure in addition to this improvements and made in the way memory modules were assembled. àDIPP: In the earliest days of computers memory was installed in a single chip at a time using a package called a “dual inline pin package (DIPP)”. The limitation of this package was that only a single DRAM chip fit onto it. àSIPP: the first attempt at combining multiple DRAM chips into a single module resulted in a single inline pin package(SIPP).  The chip were mounted on circuit boards. The design took up less space on the system board. But installing these modules was difficult. àSIMM: SIPPs were replaced by a package called “single inline memory module”. This memory board used a 30 pin connector and about 3.5* 7.5 inches in size. In most computers we have to install two SIMMs to get 16MB total RAM. As system bus could handle 16 bits at a time. àDIMM: AS PROCESSOR GREW IN SPEED AND BANDWIDTH CAPABILITY the industry adopted a new standard that is “Dual in line memory module”. Dimm from being inserted backward in the socket, and identifies the voltage of DIMM and its underlying technologies. MEMORY TYPES: FPMDRAM:  the earlist types of DRAM wre compatible with slower CPUs. When CPUs became faster, it became necessary to speed up the data transfer from memory to CPU. The first improvement is “first page mode” DRAM. FPM is differed from earlier DRAM in how data was accessed. For every request the CPU made for data RAS  find the appropriate row then  CAS locate the required data. EDO DRAM: extended data out DRAM came in 1994 and is very similar to FPM it is about 5% faster than FPM as there is no delay between read operations. It does not wait for al the processing of the first data before continuing to the next one. As soon as the address of the first data is located EDO RAM start looking for the next data. Maximum transfer rate to L2 cache is approximately 264 MBps. SDRAM: release of synchronous DRAM changed the basic architecture of the DRAM that is a large portion of the memory control chip circuitry, has been moved from the chipset to the SDRAM module itself. Now information in RAM is available to the CPU on every single clock cycle. DDR SDRAM: Double data rate synchronous dynamic  RAM is just like SDRAM except that it has higher bandwidth, meaning greater speed. Maximum transfer rate to L2 cache is approximately 1,064 MBps. RDRAM: Rambus dynamic random access memory designed by Rambus technologies, in cooperation with intel corporation. RDRAM uses a Rambus in line memory  module which is similar in size and pin configuration to a standard DIMM. It uses special high-speed data bus called the rambus channel. VRAM: Video RAM, also known as multiport dynamic random access memory is a type of RAM used specifically for video adapters or 3D accelerations. SGRAM: Synchronous graphics RAM is a less expensive approach to speeding up memory, access for graphics functions. It is not dual-ported as is VRAM therefore cheaper but performance is somewhat lower .#SYSTEM RESOURCES: ‘System resources ‘ are resources that are electrically used by hardware, allocated by firmware and then used by software. There are several devices and applications which may attempt to use the same resource and cause trouble. The four areas that can suffer from resource conflicts are memory addresses, I/O ports, IRQ lines, and DMA channels. *DMA CHANNELS: the best way to speed up system performance is to relieve the microprocessor from all its housekeeping activities. Among them more time consuming is moving blocks of memory inside the computer. For example shifting bytes from a hard disk to main memory. The DMA channel was originally designed for such purpose. It is used to transfer data to and from memory using a chip/device DMA controller without going through the main processor. This specialized chip only needs to know the location of bytes to be moved, the address to go and no. of bytes to move once. Once it receives these information from the processor the DMA controller takes control and does all that job itself. The following table summarizes functions that are commonly for 7 DMA  channels. DMA channel , Data width, Function.  0 , 8 or 16bits, Audio; 1,8 or 16 bits, Audio LAN; 2, 8 or 16 bits, Floppy Disk; 3, 8 or 16 bits, LPT; 4, 16 bits, Cascade Channel; 5, 16 bits, Not assigned; 6, 16 bits, Not assigned; 7, 16 bits, ISA IDE(HDD Controller).// DMA channels have configuration problems as fewer devices use them therefore fewer problems occur. On the other hand, no software tool can detect DMA usage and the hardware tools can detect DMA usage only for ISA  cards and devices. For this reason, it is even more important to read the hardware documentation thoroughly. *IRQ INTERRUPT REQUEST LINE: the purpose of IRQ line is to provide the system with a way to allow a device to work in the background and request the CPU’S attention when it is needed. Many devices use this resource but not all. Usually, if a device is designed to perform tasks independent of the CPU, it will need an IRQ line to alert the CPU when task is done or attention is needed. A mouse and a network card are devices that always use an IRQ. // to extend the capabilities of the interrupt system PCs use an interrupt controller chip to manage several interrupt signals and sets priority for which interrupt is serviced first. On the original IBM PC  the 8259 IRQ controller chip is used. This chip handled only 8 interrupt signals numbered 0 to 7 and assigns each one in a decreasing priority as the numeric designation increases. The interrupts assignments are as follows. IRQ No, Function, IRQ No, Function. 0, timer, 4, com1/com3; 1, keyboard, 5, Hard Disk; 2, EGA display, network, 6, Floppy disk; 3, com2/com4, 7, LPT1; // these 8 bit bus survived inside many Pc’s until a few years ago. Later it is proved that for complex systems 8 interrupts are inadequate. When IBM introduced its advanced technologies “ Pc-at” added a second IC chip 8259 to the motherboard and nearly doubled IRQ  numbers. The 2 nd chip was cascaded to the first one in such a way that output of the new chip connected to the input of the old one, the output of which in tern connected to the microprocessor, this arrangement continued though the latest Pentium type system. Following figure shows total IRQ and its function(fig). example:  the following example of modern communication illustrates how interrupts works, and when they are used. For example a file through internet has to be downloaded. First the program has to be split into two parts. So that one part could perform user tasks in the foreground. While the second part the file download routine could be written as a separate program, calls an” interrupt service routine(ISR) that could run in the background. When the first character of the download comes in. it would cause the following actions: 1. the serial port receives the character from the modem and turns on the appropriate IRQ line. 2. The IC chip on the motherboard passes it on to the CPU if no other interrupts in progress, or pending IRQ of higher priority. 3. when the CPU sees an  IRQ, it stops the foreground task at the end of the current instruction and saves the location of the next instruction to be run for the foreground task. 4. the CPU queries the IC to find out which ISR should be run and there turns control over to that ISR. 5. the IS disables any further interrupts while it is in process and save any interval registers that may modify in the next step. 6. the ISR gets the charcter from the serial port and sends it to the file system. 7.  the ISR finishes by restoring internal registers saved previously and re enables interrupts as control return to the foreground task. 8.  The foreground task continues with the next instruction by restoring internal registers saved before the interrupt. *Sharing IRQs:  When IBM first designed the PC,  the designer’s original intent was to allow IRQs to be shared. The ISA compatibility bus made this provision by allowing two devices to use the same interrupt to draw attention of the microprocessor. The newer bus standards included in their design that all cards must be able to share IRQ s but also must be configurable through software, so that if a conflict occurs software could change the resource and solve the problem. IBM initiated this technique with its MCA bus, which was also used by EISA and PCI. *IO PORTS: every device in Pc uses at least one I/O  port address. In most cases a single device uses 4,8 or 16 I/O port addresses. These port addresses are used to do the following 1. send commands to the device. 2. set, check and clear device interrupts. 3. get device information and status. 4. send and receive data. // I/O port conflicts problems is usually with the older ISA cards. When an ISA  card or device is installed that can neither report its I/O port usage nor be configured by the BIOS. Newer ISA cards that are PnP compatible can be automatically reconfigured by the O/S and usually not involved in conflicts. // I/O port conflicts are similar to memory address conflicts. Actually I/O port addresses signals are carried on the same wire as the memory address bus, with one additional wire to tell the CPU THAT it is an I/O operation not a memory operation. This is referred as IO/MEM wire. The first 10 bits of address bus are used to specify the I/O port address. Which allows for 1,024 distinct addresses.000h through 3FFh. #ARCHITECTURE OF PENTIUM PROCESSOR:  (fig):  CPU registers: these  are small groups of RAM bits inside the processor, which hold the data that is to be operated on by the ALU or FPU. The size of the register is responsible for the type of data and instructions that can be used by the processor. Early models in the PC family had 16- bit CPU registers, they could only run 16 bit software such as  DOS and Windows 3.x the 80386 was the first model to contain 32 bit CPU registers and so it could run 32 bit software. All 386, 486 and the first Pentium CPUs were limited to 32 bit registers, while the Pentium MMX and later Pentium II CPUs had some additional 128 bit registers that allowed the ALU to operate on multiple 32 bit registers that allowed the ALU to operate on multiple 32 bit numbers with a single instruction. This  technique is called “ single instruction, multiple data”. Arithmetic/Logical Unit: this is the heart of every CPU. The ALU is the part that actually performs each instruction such as fetch data from memory into a register, store data from a register to memory, perform an arighmetic or logical function on the data in a register, cause a program action based on the data in a register. Earlier generation processors 8088 and 286 would take several clock cycles to perform each instruction, later ALU designs are able to perform one or more instructions per clock cycle. Instruction decode Unit: this is the portion of the CPU that actually decodes the instruction as it comes into the processor. The newest Pentium designs actually include multiple instruction decode units, to decode instructions from multiple ALUs. Bus control Unit: the bus control unit is simply the portion of CPU that controls activity on the external bus of CPU. This portion of the CPU direct interfaces to the mother board so always runs at motherboard speed. Floating Point Processing Unit: from the 8088 through the 80386, the FPU was an external chip that was plugged into its own socket. Form the 486,m all CPUs except 486SX have the FPU built into the CPU core. Level -1 Cache and Level -2 Cache: a memory cache is used to keep track of the most frequently and most recently used locations from the slower main memory. When the cache contains the data needed by the CPU, there is no waiting and it is called ‘cache-hit’. When the cache does not contain the data it is called ;’cache-hit’ then CPU have to wait until data is delivered y slower main memory. // initially, 386 motherboard designs used 64K SRAM as ‘motherboard cache’ and yielded 9-0 percent cache-hit rate. Next generation of processor chip and mother board is no longer used. // in the Pentium and later processors the level -1 cache was spitted into two parts. I cache dedicated to hold instruction only and D cache. Dedicated to hold data only. It is more efficient than using a single large cache for both instructions and data. The latest Pentium II, III and 4 CPUs are having 1.1 and 1.2 cache in the CPU itself not on the mother board. Front-side Bus: from Pentium II, the bus connection between the CPU and the mother board has received a new name the  front side bus. More recent developments with advanced motherboard DRAM designs called RDRAM and DDR-SDRAM have resulted in some newer terms and specifications for the FSB. DDR-SDRAM is currently available for 200 MHz and 266 MHz FSB speeds. RDRAM is available in FSB speeds of 600, 700 and 800- MHz. Back-side bus: the back side bus is simply a complement to the front side bus for the level-2 cache. While front-side bus describes the interface between the level-2 cache on the processor to the mother board, the back side bus describes the interface between the level-1 cache in the processor core and level -2 cache. #THE IDE INTERFACE:  the peripherals/components must be interfaced to the host system so that they may communicate with each other. Drives are considered to be peripherals and need interface to connect with the computer. Integrated drive electronics (IDE) is most cost effective interface scheme that can support hard drives, CD-ROM drives, DVD-ROM drives and almost any other drive devices. // IDE interface underwent several distinct stages of evolution between the time of first hard cards and the drive systems used today. àThe ATA standard: the IDE interface has many names. The original name for the interface used by IDE drives is the “AT attachment (ATA)” interface named for the IBM AT computer that first introduced the 16 bit ISA bus. Today the ATA interface is the industry standard. The ATA standards are designed by Technical committee T13 of the national committee on information technology standards the T13 committee is an independent association of representatives from major manufacturers of PCs, storage devices and other computer components. à The ATA-2 standard: this standard was published in 1996 and approved by ANSI called the “AT attachment interface with extensions”. Along with ATA-2 is largely regarded as a significant improvement to ATA1 it defines faster PIO DMA data transfer modes. The standard adds more powerful drive command such as the identified Drive command to support auto identification in CMOS. The standard also introduces power management functions, block mode data transfers. àATA-3: the ATA-3 standard was published in 1997 and was approved by ANSI called “ attachment -3 interface” its intension is to increase the reliability of the IDE interface  by introducing the use of bus terminator at both ends of the IDE cable to reduce noise. #THE SCSI INTERFACE:   the small computer systems interface (SCSI) is the second most popular PC drive interface. It is generally considered as more devices and more types of devices. Scsi is better suited to network environment. SCSI was originally designed to be a hard drive interface but supports other types of devices came later. àthe SCSI bus: scsi devices are connected to the host adapter in a daisy chain fashion internal devices use a single rigbon cable with multiple in connectors. One among them connects to the internal connector on the adapter and the rest of which connects to the various devices inside the computer. Where as external devices have two connectors on them and they use separate SCSI cable to connect first device to the external connector on the host adapter, the second device to the first and so on. à SCSI ids: IDE channels are limited to two devices because they use a simple binary circuit to differentiate between the two. Commands intended for one device have a value of 0 on that circuit and commands for the other have a value of 1. where as SCSI can have a total of 8 or 16 devices on the bus depending on its type. // the ID s assigned to the devices on  SCSI bus can be important to the performance of the system, because the ID indicates the priority with which the device is granted access to the bus. Higher numbers have the higher priority. Similarly IDs assigned to devices should be based on their functions, relative speeds and their importance to the system. #SCSI Vs IDE   1. ultra 3 wide SCSI  runs at 160 MB/sec and Fast ATA/66 IDE runs at 66 MB/sec. 2. IDE is basically hard drive interface but can accept other types of devices. SCSI was designed to accept a wide variety of internal and external devices. 3. IDE is single threaded interface means it can only handle one command at a time. If two processes are accessing different devices on the same IDE channel they have to access the system alternatively. 4. copying data from a hard disk to a CD using one IDE channel requires the system to continually access one device and then the other whereas SCSI devices can both be running at the same time. 5. IDE can perform excellently and provides access to basic peripherals like CD-ROM drives. SCSI is the better choice network systems when we want to connect lot of devices to the system.